This description relates to a set-up voltage generating circuit and a plasma display panel (PDP) driving circuit using same configured to generate a set-up voltage by way of a method of charging a predetermined capacitor using a sustain voltage Vs without recourse to a DC/DC converter in forming a set-up voltage necessary for a set-up period of the PDP.
Recently, Plasma Display Panels (PDPs) have gained popularity as the next generation flat display devices. The PDPs are applied to various fields such as wall hanging televisions, displays for home theaters and monitors for work stations because they can be excellently implemented with a large dimension screen and a thin profile.
A driving apparatus for a color three-electrode Alternating Current (AC) surface discharge PDP will be briefly described with reference to FIG. 1.
Referring to FIG. 1, the three-electrode AC surface discharge PDP 11 in the related art includes Y electrodes Y1 through Ym, Z electrodes Z1 through Zm, each alternatively arranged one at a time and in parallel. The Y electrodes (Y1˜Ym) and the Z electrodes (Z1˜Zm) are respectively referred to as scan electrodes and common electrodes.
Furthermore, address electrodes A1 through Ak are arranged, being orthogonal to the respective Y electrodes and the Z electrodes with a predetermined space formed therebetween.
A cell is formed at every intersection between Y electrodes Y1 through Ym and the address electrodes A1 through Ak. Through the structure thus mentioned, a screen is constructed in such a manner that the cells are formed displaying any one of R (red), G (green) and B (blue) at each intersection arranged in a matrix.
Referring again to FIG. 1, a Y driving unit 12 supplies sustain pulses and scan pulses to each Y electrode Y1 through Ym, each corresponding to the Y electrodes of the PDP 11.
A Z driving unit 13 supplies sustain pulses and scan pulses to each Z electrodes Z1 through Zm, each corresponding to the Z electrodes of the PDP 11. An address driving unit 14 supplies writing pulses to each address electrode A1 through Ak, each corresponding to the address electrodes A1 through Ak of the PDP 11.
A controller 15 serves to digitalize an analog image inputted from outside, outputting a digital image, and generates various control signals in response to control signals inputted from outside including clocks, horizontal synchronous signals (HS) and vertical synchronous signals (VS) to thereby control the Y driving unit 12, the Z driving unit 13 and the address driving unit 14.
FIG. 2 is a driving circuit diagram of a Y driving unit according to the prior art and FIG. 3 is a waveform diagram illustrating each terminal voltage of a PDP.
Now, a driving circuit 200 of a Y driving unit of the PDP according to the prior art will be described with reference to FIGS. 1 through 3.
First, a graph Y denotes an output of the Y driving unit 12, a graph Z represents an output of the Z driving unit 13, and a graph X shows an output of the address driving unit 14. The driving circuit 200 is included in the Y driving unit 12, and description will be centered on the graph Y out of the graphs of FIG. 3.
Transistor Q5 and Q3 are turned on during a setup period (a) in FIG. 3, and a sustain voltage Vs is supplied from an energy retrieve circuit 23.
The sustain voltage Vs supplied from the energy retrieve circuit 23 is supplied to each Y electrode Y1 through Ym via an internal diode of the transistor Q3, a transistor Q4 and a transistor Q9 of a scan integral circuit (IC) 22. As a result, the voltage of the Y electrodes Y1 through Ym abruptly rises to the sustain voltage Vs, as shown in a setup period (a) of FIG. 3. At this time, the scan IC 22 functions to directly apply a wave voltage generated in response to an operation of the driving circuit 200 to any one electrode of the Y electrodes Y1 through Ym of the panel 11.
Meanwhile, a drain terminal of the transistor Q5 is applied with a set-up voltage Vsetup. The transistor Q5 whose channel width is adjusted by a variable resistor VR1 increases a voltage of a node N1 to a predetermined slope to raise the voltage to the set-up voltage Vsetup. Consequently, the driving circuit 200 supplies the set-up voltage during the set-up period (a). The set-up voltage is supplied to each Y electrodes Y1 through Ym via the transistor Q9 of the scan IC 22 and the transistor Q4. The Y electrodes Y1 through Ym are applied with a rising ramp waveform ramp-up.
After each Y electrode Y1 through Ym is applied with a rising ramp waveform ramp-up, the transistor Q5 is turned off. Once the transistor Q5 is turned off, only the sustain voltage Vs supplied to the energy retrieve circuit 23 is applied to the node N1, and as a result, each Y electrode Y1 through Ym abruptly falls to the sustain voltage Vs.
Henceforth, the transistor Q4 is turned off at a set-down period (b) illustrated in FIG. 3, and a transistor Q6 is simultaneously turned on. The transistor Q6 is adjusted at a channel width thereof by a variable resistor VR2 and the voltage of node N2 falls by a predetermined slope up to a set-down voltage −Vy. At this time, a falling ramp waveform Ramp-down is applied to each Y electrode Y1 through Ym.
The transistor Q4 is disposed with an internal diode having a direction different from that of the transistor Q3 to prevent the voltage applied to the node N2 from being supplied to a base potential GND via the internal diode of the transistor Q3 and the internal diode of a transistor Q2.
Transistors Q10 and Q11 supplies a scan reference voltage Vsc to the Y electrodes Y1 through Ym (not scanned in the scan process) in an address period.
Meanwhile, the set-up voltage Vsetup is generally higher than the sustain voltage Vs. In order to generate the sustain voltage Vs, a DC/DC converter 21 was used with a sustain voltage Vs at the primary side. In other words, the set-up voltage Vsetup is always higher than the sustain voltage Vs, such that the DC/DC converter 21 was used to generate the set-up voltage Vsetup by way of the sustain voltage Vs.